With just a week to go before the London Low-Latency Summit, I thought it was the right time to preview what the agenda will bring. Space at the new venue – the America Square Conference Centre – is limited but there’s room for a few more delegates, so be sure to register today. Now, with the public service announcement/commercial over …
Firstly, it will be interesting to hear from Shawn Edwards, CTO of Bloomberg. It’s not a vendor one associates much with the term low latency, though they’ve quietly been making moves to re-engineer their network and leverage co-lo facilities at the likes of Equinix in order to provide much faster market data. They also recently announced plans to open source their data and transaction APIs in order to get application developers to use them. It’s all part of a strategy to own the enterprise, as well as the desktop. And that will include the low-latency enterprise.
Expect to hear some ultra-low-latency news from TIBCO Software’s EMEA financial services messaging chief Vasil Kajcovski. A technology update for sure. Perhaps some new benchmarks of its FTL middleware running on Intel’s Sandy Bridge chips?
There are a couple of killer morning panels – OK, moderated by yours truly – that will give a big picture view of some topical subjects. One will focus on the different requirements for latency for different markets and trading strategies, and why being the fastest isn’t always worth it. Another panel will explore the dreaded jitter phenomenon – what causes it, how to deal with it, how to avoid it completely.
The afternoon is when things get pretty technical, with a number of drill-down workshops. Corvil will focus on inter-party latency, which should soon see an announcement from the FIX peeps. And TS-Associates will join with Korusys to discuss precision time and why it’s needed.
The nitty gritty of co-lo, proximity and connectivity will be discussed by Equinix and Vello Systems. And Gnodal, Stordis, LSI will delve into network switching and in-memory acceleration.
Of course, the world of FPGAs will be a part of the day. Both Fiberblaze and Maxeler will outline strategies for implementing complex logic – not just I/O and data parsing – in silicon. That’s going to be the next big thing for hardware acceleration, methinks.
Oh, and there are exhibits, and lunch, and coffee (and cake) and even a beer or two at the end. If you’re not there next Tuesday, then I guess you’re a reference data kinda person. Poor thing.