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STAC Points to Everest Boost

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Via a report sponsored by data feed handler specialists SR Labs, the benchmarkers at STAC have just announced data for initial tests run on Intel’s recently-introduced Everest chip. Compared to Intel’s standard Westmere chip, one data point suggests a 22% reduction in mean latency.

Everest – or Intel’s Xeon X5698 – is a dual core chip, with each core running at 4.4 Ghz, compared to the X5687 (aka Westmere), with four cores at 3.6 GHz. Intel describes Everest as an “off roadmap” chip designed for “very specific, niche high performance computing applications” while still “running within warranty covered norms, specifications and safe thermal envelope.”

The tests were run using SR Labs’ MIPS (Market Data In Process System) feed handling software. While multi-core chips are often leveraged to boost application performance, some applications are inherently single-threaded, and so benefit more from increased speed of each core. Market data feed handlers and exchange matching engines are two such applications.

For the geeks, the two “stacks under test” comprised:

– SR Labs MIPS In-Process Market Data Line Handler for TVITCH 4.1 
– CentOS 5.5, 64-bit Linux 
– IBM x3650 Server 
– Myricom 10G-PCIE2-8B2-2S Network Interface 
– Processor: 
SUT A: 2 x quad core Intel Xeon 5687 3.60 GHz (“Westmere”) 
SUT B: 2 x dual core Intel Xeon 5698 4.40 GHz (“Everest”)

The test harness for this project incorporated TS-Associates’ TipOff and Simena F16 Fiber Optic Tap for wire-based observation, along with TS-Associates’ Application Tap cards for precise in-process observation. A Symmetricom SyncServer S350 was the time source for the harness.

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