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Xilinx Seeks to Democratise FPGA in Trading with Accelerated Algo Framework

FPGA pioneer Xilinx has launched what it reckons is the industry’s first hardware-based algorithm trading solution stack in a bid to make FPGAs more accessible to the marketplace.

Xilinx Accelerated Algorithmic Trading, a new algorithmic trading reference design, will provide traders, market data providers and algorithmic trading platforms with a modular and open-source solution, to enable software-based development techniques to be used on FPGA hardware, for sub-microsecond trading strategies.

The new framework builds on the launch of the company’s Alveo data centre accelerator cards in 2018 and the introduction of its Vitis open-source software development platform in  2019.

According to Alastair Richardson, Head of Global Business Development for Financial Technology at Xilinx, “This is the first time a vendor has created a full hardware-based algorithmic trading solution stack, and done it in a commoditized way that is accessible and available to the whole market.”

Whereas the use of hardware-accelerated trading has become de rigueur among high frequency trading firms, until now FPGAs have not been adopted by the wider market because of high and costly barriers to entry. Xilinx aims to change all that by providing a full suite of ultra-low latency algorithmic trading components on commoditised hardware, which can be tailored to suit an individual firm’s specific needs. Use cases highlighted by the company include market data feed handling, FIX gateways, smart order routing, pre-trade risk, option pricing and various algo trading strategies such as Peg and VWAP (volume-weighted average price).

Xilinx claims sub-microsecond tick-to-trade speeds out of the box, based on CME data. This includes receiving market data packets from the CME, running the feed handler, building an order book, creating a Peg algo and creating and sending an order back to the exchange.

One of the key features of the solution is that firms can augment Xilinx’s pre-defined IP blocks with their own, without having to write FPGA-specific code. “You can programme it all in C and C++ style languages,” says Richardson, “so it’s open to a much wider audience. All of our libraries are open sourced, so you can download them off and start compiling, with no licence fees. And the algorithmic trading framework has all the IP that you need to get going and start porting your application from CPU onto FPGA. This means that a much wider variety of software ISVs and in-house developers can make that jump from CPU onto hardware. We’re enabling the whole industry to take advantage of this through a democratised framework, allowing low latency networking and acceleration for all”.

Richardson explains that the pre-configured IP blocks give an example of what is possible, but that most firms will want to adapt the solution to suit their own requirements. “We recognise that firms have their own pricing engines, we don’t want to tell you how to write your algorithms. But we do want to show you what’s possible and how to do it, and give you that kickstart that you need to start moving in this direction. The example design is for tick-to-trade on the CME, so you can plug it in, give it a go, see how it works, how it handles and receives market data and sends an order back to the exchange. We’ve already had some initial customers convert this design from the CME to other exchanges in a matter of weeks, not years, which is the traditional development time on FPGA”.

Richardson adds that while the initial design is for tick-to-trade, the IP blocks can be altered so that firms can, for example, use the same framework to receive orders, run pre-trade risk checks, and send orders out to the market.

The framework also allows for integration with in-house or third-party vendors such as Enyx and LDA, says Richardson, and can be run as a hybrid model. “Because it allows you to use both the CPU and the FPGA, you can offload just a specific function,” he says. “You could, for example, offload the market data component, so all market data filtering is done on the FPGA and everything else sits on the CPU. Then, as you get more comfortable, you may want to migrate more latency-sensitive portions of your application into a full hardware implementation. The design accommodates and allows you to do both, and to benefit from Xilinx upgrades, so you’re future-proofing your development.”

How easy is it to get started with the framework?

“You can go out today and buy an Alveo U50 or U250 through your OEM channels, like Dell, HP, Lenovo, and Supermicro,” says Richardson. “Then just go and download it from, it’s free to try. You don’t even need a card to get going, you can run some of these designs and examples in the cloud and then port to an on-prem solution once you’ve got a suitable design up and running.”

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