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The leading knowledge platform for the financial technology industry

A-Team Insight Blogs

Q&A: Ron Huizen of BittWare on Accelerating FPGA Development

BittWare was in the news recently with its FPGA network boards being adopted by Fixnetix for its trading and pre-trade risk offering. As well as providing hardware, BittWare’s also has tools to speed up FPGA development, helping to overcome a much-cited drawback of adopting them. talked to the company’s vice president of technology Ron Huizen to find out more.

Q: Fixnetix recently announced that they are leveraging your technology. What are you providing them?

A: They are currently using our Altera Stratix V-based PCIe board, the S5-PCIe (see our product information here) and are looking at our upcoming PCIe boards (see more here).

Q: Can you describe some more the capabilities of your S5 PCIe cards?

A: Our S5 family of boards all feature the Altera Stratix V FPGA, which is the highest performance FPGA available, and well suited to the financial industry.  We have two QSFPs on board, so can handle 8 lanes of 10gE, which go straight to the FPGA (no external PHY) for the lowest possible latency. The QSFPs can also support 40gE, so that future proofing is built in. We’re running PCIe Gen 2 for most people right now, but support for Gen 3 is also built in, so when those slots are more widely available, we can fill them.

We have various memory configurations, as different applications have different needs, from large bulk memory like DDR3 SDRAM, to low and deterministic latency QDR II and QDR II+ SRAM for things like look up tables. We are also working on RLDR3 (Reduced Latency DRAM), which is reduced latency compared to SDRAM, but higher than QDR.

Finally, we have options to add our Anemome co-processor chip, which can add a tremendous amount of C programmable processing to the boards.

Q: Why choose Altera as your FPGA supplier? How does the Stratix V compare to their earlier devices – what is the roadmap for them?

A: We decided several years ago to work exclusively with Altera. This was based both on their excellent technology (underlying FPGAs and tools) and on being great to work with (partnerships and support). We’re not a huge company, so we prefer to develop close relationships and expertise with a few partner companies as opposed to trying to cover everything. Also, being exclusive means we can have a very close relationship with Altera, as they are not concerned about us sharing their secrets with their competition.

The Stratix V is the next step forward in FPGAs – faster transceivers, faster fabric, more DSP resources, and lower power. These all combine to provide an ideal platform for financial applications. There will of course be a next generation, but right now, this device is the cat’s meow for this industry, as can be seen by the tremendous acceptance it is getting.

Q: How does your Atlantis FrameWork offering assist companies – like Fixnetix – to develop applications based on FPGAs?

A: We provide not only a working board, but the underlying building blocks needed so that our customers can focus on their expertise, which in this case is their financial applications. We provide cores for all the physical aspects of the board, from memory controllers to the high speed transceivers, as well as software interface libraries and drivers to move data and control the board.

In talking to customers who in the past developed their own FPGA boards, they’ve estimated they spent 80% of their effort getting to the point where they could start working on their actual application. Our goal is to save our customers this 80% so they hit the ground running and get to market faster.

Also, we will have a new board available as soon as the next generation FPGA comes out, and we make it easy for our customers to move their application to the next gen board, so they know that they can get technology refreshes every few years for minimal development.

View this video to learn more about Atlantis.

Q: How are other trading firms using your products. Are there particular financial markets requirements that differ from the other verticals that you sell into?

A: We have a variety of financial customers, and they tend to fall into two camps. The first is network based, so are using the multiple 10gE (and soon 40gE) lanes. Their use can range from just being an intelligent NIC (offloading the CPU by doing things like filtering and TCP/IP), to doing pretty much the whole application in the FPGA, with the CPU just providing some minimal supervision.

The other group is using the board as an acceleration engine for large computations (like risk analysis), so really the competition here is between FPGA, GPUs, and CPUs.

A difference with other verticals from a technical requirements perspective is the low latency through the whole system for the network based applications. We deal with low latency in some other verticals where feedback loops are used, but in many systems, the overall performance and throughput matters more than latency. From a development perspective, the huge difference is the speed at which this market adopts and deploys technology. We were used to our commercial and telecom markets being faster than our mil/aero markets, but this financial market makes the telecoms look slow.

Q: You probably saw the recent Arista announcement – FPGAs in routers. How do you expect systems architects to exploit the various FPGA deployment options in the future in their designs.

A: Well, they certainly are being given more and more tools to make use of. It’s been our experience that no one technology can be optimal for all applications, so there is always room for new approaches, and there are many very clever system architects who will think of ways of using technologies for things they weren’t initially developed for.

One technology area that is very interesting, and will certainly affect how FPGAs are deployed, is the work being done by Altera in OpenCL to make FPGAs more accessible to traditional software based firms.

Another very interesting technology is our Anemone co-processor chip, which I mentioned earlier. This is a C programmable, multi-core, low power floating point co-processor. It sits directly connected to the FPGA, and provides tremendous floating point processing at low power (current generation is 24 GFLOPS in 2 watts) as well as C programmability. We’re working with our financial customers to see how this can be exploited in their applications.

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