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NovaSparks Adds Data Feeds; Outlines FPGA Matrix Architecture; Details Performance

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NovaSparks has added support for an additional five data feeds to its Gen2 appliance, while at the same time outlining the FPGA matrix architecture that the appliance implements in order to handle multiple feeds and application functionality, and detailing its latency profile.

The new data feed support comprises feeds from Bats (BYX and BZX), Direct Edge (NG-A and NG-X), NYSE Arca, the London Stock Exchange (Level 2) and Turquoise (Level 2). Support for Nasdaq, CME and Eurex was already available. NovaSparks says the choice of the added data feeds was driven by customers, though it is currently focusing on providing support for equities and futures exchanges in Europe and North America.

Gen2 is a 2U rackable appliance based on FPGAs from Altera – up to three per appliance. Multiple appliances can be inter-connected to scale up the matrix to support multiple data feeds and trading functions.

The company has released data detailing the latency profile of its matrix architecture. “Our FPGA Market Data Matrix Feed Handlers process the cash equity feeds in less than 700 nanoseconds even during micro bursts and message volumes peaks,” says NovaSparks CEO Yves Charles.

The chart below details the latency observed when a full day of ITCH message data – some 280 million packets – is replayed in just eight minutes.

 

NovaSparks attributes the consistency of latency under load to the matrix architecture’s  implementation of a full set of functions in multiple FPGAs, as opposed to other approaches where FPGAs are used simply for basic acceleration, such as network protocol handling and data transformation, while most of the processing is performed on a traditional CPU.

In the NovaSparks architecture, FPGAs are used for UDP, IP and network handling, message parsing, symbol filtering, book building and fan out to downstream applications. Yves says that the company will this month roll out a proof of concept implementation running trading algorithms on FPGAs within the matrix.

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