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xCelor Taps Arista Application Switch for FPGA-based Ticker Plant, Pre-Trade Risk

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Chicago-based market data feed specialist xCelor is getting set to release ticker plant and pre-trade risk functionality running on Arista Networks’ 7124FX Application Switch. The switch combines a Stratix V FPGA from Altera with a network switch for data processing as close to the network as one can get.

The company is currently testing its Ticker-Plant-in-a-Switch (TPS) product, which receives and normalises raw market data as it is being switched, with end-to-end latency of around 1.5 microseconds. Such an architecture removes the typical requirement for data to pass in and out of network interfaces for processing on a traditional CPU in a server, which generally results in several microseconds of latency.

As well as normalisation, TPS can also filter raw feeds by symbol, so that just data subsets are passed to down range systems, or transmitted via wide area links. In addition to reducing latency, TPS saves on power and rack space, important considerations for co-located systems.

A planned extension to the TPS is Market Data over Microwave (MDoM) functionality, which will use the symbol filtering in the TPS, and add additional compression and additional redundancy for transmission over bandwidth-limited microwave links. The bandwidth saved is used to extend redundancy, and MDoM can arbitrate between microwave and fibre to ensure no lost data. CFN Services is looking to deploy MDoM in its microwave offerings.

Also in the works is a Risk Evaluation Module (REM), a “bump-in-the-wire” solution for the SEC’s 15c3-5 pre-trade risk rule. REM can perform risk checks on Ouch format order messages as they are being directed to an exchange, with exchange-native rejects on breach. This approach allows for ‘plug in’ implementation of REM into existing trading systems.

For both TPS and REM, switching using the FPGA on the 7124FX can be performed faster than the native Fulcrum ASIC chips built into the device, allowing additional logic to be implemented without any great impact on overall latency.

xCelor began life about 18 months ago with a focus on building FPGA-based data feed handlers.  To date, is has rolled out implementations based on PCIe cards, hosting a Xilinx Vertex 6 FPGA. Supported feeds include those from Nasdaq, NYSE Arca, Direct Edge and Bats Global Markets. An implementation for CME data is expected next month. The company is also working to implement Stratix V versions of its PCIe cards, and is looking to reduce processing latency from their current 700 nanoseconds.

Commenting on implementing logic on both Altera and Xilinx FPGAs, xCelor CTO Robert Walker offers: “Both platforms have many similarities but also many differences. If the possibility of later porting is considered at the design stage this can simplify the process significantly. Even so, some things must be rewritten completely to get them to work. The HDL code itself is supported very well by both platforms – so compiling pure hardware code for either platform is no problem at all. However, the IP cores such as Altera’s NIOS II and Xilinx Microblaze processors, their supporting of peripheral devices (memory controllers, timers, networking subsystem) as well as their development environments are completely different.  This means that if your design relies on one or more soft processors it can be a real challenge!”

Walker sees switch-based FPGA processing as an important and useful emerging architecture: “Putting logic on the switch opens the doors for many other applications. Sometimes you know what you want to do in certain circumstances; under certain market conditions. What if we could prime orders on the switch to be triggered when certain market conditions arise? A simple example: ‘Send this buy order when the price of MSFT drops below 30.62’. Imagine if you could program this into the switch: you could go from tick to trade in nanoseconds. This is exciting stuff and it will be reality very soon!”

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