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Enyx Integrates Xilinx FPGA Technology to Power nxFeed

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Enyx has increased the performance of its nxFeed solution on the back of a new release of its FPB2 platform that is powered by Xilinx Virtex UltraScale+ (VUS+) field programmable gate array (FPGA) technology.

The FPB2 platform, developed by Bittware, uses the Xilinx VUS+ FPGA to offer a four-times larger matrix than Enyx’s previous platform, as well as 25Gb Ethernet connectivity, better overall in/out latency, and a running frequency of up to 800MHz. The platform pushes up performance of the Enyx nxFeed, a market data distribution system supporting over 40 markets across Europe, the US and Asia, by more than 30%. The Xilinx VUS+ enabled FPB2 platform will be available for production on November 1, 2017.

Enyx managing director and co-founder, Laurent de Barry, says: “Our main goal is to provide the latest FPGA technology to answer our customers’ challenges. The FPB2 platform gives clients new, advanced options with the addition of incredible performance.”

The nxFeed solution will introduce a wide range of integrated, state-of-the-art features and capabilities. Upgraded components include:

Enhanced functionality

  • More than 2x the symbol capacity
  • 18,000 symbols for by-order protocols
  • 36,000 symbols for by-price protocols
  • Improved latency by more than 30%
  • Average wire-to-wire latency of 1076 ns for Nasdaq Totalview ITCH
  • Average wire-to-wire latency of 853 ns for CME Globex MDP3

Cutting-edge features

  • Continuous trading book uncross for by-order protocols
  • Improved publication filtering and granularity
  • PTP time stamping

Improved capabilities

  • PCI Express Gen 4.0 ready
  • 25Gbs Ethernet ready

Recent client success for the Enyx nxFeed includes a strategic partnership with BNP Paribas that will see the latter using Enyx solutions for market data and market access. BNP Paribas has also selected the Enyx nxFeed product for high-performance market access in the Americas, Europe and Asia, and the two companies are teaming up to integrate their hardware acceleration technologies to improve the efficiency of real-time data processing.

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